View SM8211_1116401.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SM8211m nippon precision circuits? nippon precision circuits inc. pocsag decoder for pagers overview the SM8211m is a pocsag-standard (post of?e code standardization advisory group) signal pro- cessor lsi, which conforms to ccir recommenda- tion 584 concerning standard international wireless calling codes. the SM8211m supports call messages in either tone, numerical or character outputs at signal speeds of 512 bps or 1200 bps using a 76.8 khz system clock, or 2400 bps using a double-speed 153.6 khz system clock. note that output timing values for 2400 bps mode operation are not shown in this datasheet, but can be obtained by halving the values for 1200 bps mode operation. cmos structure and low-voltage operation realize low power dissipation, plus an intermittent-duty receive method (battery-saving function) reduces battery consumption. the SM8211m is available in 20-pin ssops. features n conforms to pocsag standard for pagers n 512 or 1200 bps signal speed n supports tone, numeric or character call messages n battery-saving function for low battery consump- tion n bs1 (rf control main output signal) and bs3 (pll setup signal) 60-step setup time setting?or bs3, 50.8 ms (max) at 1200 bps and 119.1 ms (max) at 512 bps note that (bs3 setup time) - (bs1 setup time) should be set to 3 2. n bs2 (rf dc-level adjustment signal) before/dur- ing reception selectable adjustment timing n 6 addresses 4 sub-addresses (total of 24 addresses) n 1-bit and 2-bit burst error auto-correction function (messages only) n 25 to 75% duty factor signal coverage (during pre- amble detection) n 8 rate error detection condition settings n 8 receive mode settings n 76.8 or 153.6 khz system clock (crystal oscillator or external clock input) n built-in oscillator capacitor n built-in input signal ?ter, with ?ter on/off and 4 selectable ?ter characteristics n 1.2 to 3.5 v (76.8 khz system clock) or 2.0 to 3.5 v (153.6 khz system clock) operating supply volt- age n molybdenum-gate cmos process realizes low power dissipation n 20-pin ssop pinout package dimensions 1 xvdd 2 bs1 3 bs2 4 bs3 5 vdd 6 test1 7 test2 8 tx-clk 9 tx-data 10 break 11 rst 12 rx-data 13 backup 14 sig-in 15 vss 16 add-det 17 rx-clk 18 syn-val 19 xt 20 xtn SM8211m 5.30 0.05 7.40max 0.30 0.15 1.80 0.05 0.65 0.12 0.60 0.15 7.90 0.20 7.20 0.05 1.50 2.35 0.68 0.12 4 4 0.15 + 0.05 - 0.10 0.20 0.05 1.30 0.10
SM8211m nippon precision circuits? block diagram pin description i:input o:output number name i/o description 1 xvdd oscillator circuit supply pin. capacitor connected between xvdd and vss. 2 bs1 o rf control main output signal 3 bs2 o rf dc-level adustment signal 4 bs3 o pll setup signal 5 vdd supply voltage 6 test1 i test pin. leave open for normal operation. 7 test2 i test pin. leave open for normal operation. 8 tx-clk i id data read sync clock 9 tx-data i id data input 10 break i message transmission interrupt 11 rst i hardware reset input 12 rx-data o received data output (to cpu) 13 ba ckup i power save 14 sig-in i nrz signal input pin 15 vss ground 16 add-det o address detection output. high on detection 17 rx-clk o received data output sync clock 18 syn-val o sync code detection output. high on detection 19 xt i 76.8 or 153.6 khz oscillator or external clock input pin 20 xtn o oscillator output pin receive data register flag register address register timing control digital pll preamble pattern sync code idle code data comparator xt xtn test1 test2 error correction break bs1 bs2 bs3 rx-clk tx-clk tx-data add-det syn-val rx-data sig-in vdd xvdd vss rst backup
SM8211m nippon precision circuits? specifications absolute maximum ratings v ss = 0 v recommended operating conditions v ss = 0 v dc characteristics v dd = 1.2 to 3.5 v, v ss = 0 v, t a = - 20 to 70 c unless otherwise noted 1. the consumption current is slightly higher when rst is going low. parameter symbol rating unit supply voltage range v dd - 0.3 to 7.0 v input voltage range v in - 0.3 to v dd + 0.3 v power dissipation p d 250 mw storage temperature range t stg - 40 to 125 c soldering temperature t sld 260 c soldering time t sld 10 s parameter symbol condition rating unit supply voltage range v dd 76.8 khz system clock 1.2 to 3.5 v 153.6 khz system clock 2.0 to 3.5 operating temperature range t opr - 20 to 70 c parameter symbol condition rating unit min typ max consumption current 1 i dd xt = 76.8 khz, v dd = 3.5 v 20.0 30.0 m a xt = 153.6 khz, v dd = 3.5 v 25.0 35.0 high-level input voltage (all inputs) v ih 0.8v dd v low-level input voltage (all inputs) v il 0.2v dd v high-level output voltage (all outputs except xtn) v oh i oh = - 20 m a, v dd = 2.0 v v dd - 0.1 v low-level output voltage (all outputs except xtn) v ol i oh = 20 m a, v dd = 2.0 v 0.1 v input leakage current (all inputs except xt) i il v in = v dd or v ss 1.0 m a standby supply current i dds t a = 25 c 1.0 m a
SM8211m nippon precision circuits? ac characteristics v dd = 1.2 to 3.5 v, v ss = 0 v, t a = - 20 to 70 c unless otherwise noted ac timing 1. internal digital pll operation is subject to some change. parameter symbol condition rating unit min typ max tx-clk pulsewidth t pwtx 13 100 m s tx-clk pulse cycle t cytx 450 m s tx-data setup time t stx 1.0 m s tx-data hold time t htx 1.0 m s xt pulse frequency t cyxt - 250 ppm 76.8 or 153.6 +250 ppm khz xt pulse duty cycle d xt 25?5% break pulsewidth t pwbr 13 m s rx-clk pulse cycle 1 t cyrx 512 bps 1953 m s 1200 bps 833 rx-clk pulsewidth 1 t pwrx 512 bps 124 m s 1200 bps 52 rx-data lead time 1 t srx 512 bps 1341 m s 1200 bps 573 rx-data hold time 1 t hrx 512 bps 488 m s 1200 bps 208 tx-data tx-clk rx-clk t pwtx t cytx t stx t htx t cyrx t pwrx t hrx t srx rx-data
SM8211m nippon precision circuits? functional description receive format the receive format conforms to ccir rpc no. 1 (pocsag). sync signal (sc) the sync signal is a continuous code word in the received signal, used for word synchronization. it comprises 31 bits in an m-series bit pattern plus one figure 1. receive signal format preamble 0 sc 1234567 sc sc ... 1 0 1 0 1 0 1 0 1 0 ... 1st batch 2nd and successive batches sync code word 1 frame (= 2 code words) frame number 1 code word (32 bits) continuous 576-bit "1,0" bit pattern even-parity bit, making a 32-bit signal. the sync code word pattern is shown in table 1. table 1. sync code word bit number bit value bit number bit value bit number bit value bit number bit value 1091170251 2 1101180261 3 1110190270 4 1121201281 5 1130210291 6 1140221300 7 0151230310 8 0160241320
SM8211m nippon precision circuits? code words (address and message signals) each code word comprises 32 bits as shown in table 2. call number to call sign conversion 1. the msb is the address/message code word control bit. it is 0 for an address signal, and 1 for a message signal. 2. bits 2 to 21 contain the address or message information. 3. bits 22 to 31 are bch(31,21) format generated check bits, where bch(n,k) = bch(word length, number of information bits). 4. the lsb is an even-parity bit for bits 1 to 31. this conversion expands a 7-digit decimal call num- ber into a 21-bit binary call sign, as shown in ?ure 2. after expansion, the high-order 18 bits are assigned to bits 2 to 19 (address signal), and the low-order 3 bits are the user-de?ed frame identi?ation pattern, which is stored in id-rom. the two function bits de?e which of four call functions is active. table 2. code word format code word bit number 1 (msb) 1 2 to 19 2 20, 21 2 22 to 31 3 32 (lsb) 4 address signal 0 address bits function bits check bits even-parity bit message signal 1 message bits check bits even-parity bit 20 21 function 0 0 a call 0 1 b call 1 0 c call 1 1 d call figure 2. call number to call sign conversion 1 7-digit decimal call signal (gap code) bits 2 to 19 (18 bits) 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 20 21 32 1 bits 22 to 31 (10 bits) msb lsb 21-bit binary conversion call sign frame identificaton pattern function bits bch(31,21) generated check bits flag: 0 = address signal 1 = message signal even-parity bit (for bits 1 to 31)
SM8211m nippon precision circuits? idle signal (dummy signal) an idle word can be inserted into either the address or message signal to indicate that the word contains no information. the idle word bit pattern is shown in table 3. message reception is halted when the receiver detects an idle word. in pager systems that send numeric data, the number of frames varies with the type of message being sent. in this case, an idle signal is transmitted to indicate completion of the message. receive signal duty factor during preamble detection, the preamble pattern (1,0) is recognized at duty factors from 25% (min) to 75% (max) of the (1,0) preamble cycle. battery saving (bs1, bs2, bs3) the SM8211m controls the intermittent-duty opera- tion of the rf stage, which reduces battery consump- tion, and outputs three control signals (bs1, bs2, bs3). the function each signal controls in each mode is described below. n bs1 (rf-control main output signal)?he rf stage is active when bs1 is high. the rising- edge setup time for receive timing is set by ?gs rf0 to rf5 (60 steps). the maximum setup time is 49.167 ms at 1200 bps, and 115.234 ms at 512 bps. note that 3c, 3d, 3e and 3f are invalid settings for bs1. n bs2 (rf-control output signal)?s2 is used to control the discharge of the receive signal dc-cut capacitor. the function of bs2 is determined by ?g bs2, as described below. when ?g bs2 is 0, pin bs2 goes high together with bs1 and then goes low again after the bs1 setup time. however, in lock mode (during address/message reception), it stays low. when ?g bs2 is 1, pin bs2 goes high during lock mode sync code receive timing, and pre- amble mode and idle mode signal receive tim- ing. n bs3 (rf-control output signal)?s3 is used to control pll operation when the pll is used. the rising-edge setup time for receive timing is set by ?gs pl0 to pl5 (60 steps). the maximum setup time is 50.833 ms at 1200 bps, and 119.141 ms at 512 bps. note that 3e and 3f are invalid settings for bs3. note also that (bs3 rising-edge setup time) - (bs1 rising-edge setup time) should be 3 2. table 3. idle code word bit number bit value bit number bit value 1 0 17 1 2 1 18 1 3 1 19 0 4 1 20 0 5 1 21 0 6 0 22 0 7 1 23 0 8 0 24 1 9 1 25 1 100260 110270 120281 131290 140301 150311 161321
SM8211m nippon precision circuits? operating modes the SM8211m has four operating modes?witch- on, preamble, idle and lock modes. note that all values in parentheses in the following ?ures are for the case when the speed is 1200 bps. switch-on mode after power is applied and after rst has gone low to reset all internal circuits, code words for the 27-bit ?g data and the six 18-bit addresses are received from the cpu on tx-data and are stored. as each code word comprises 32 bits, this process takes (32 figure 3. switch-on mode timing 1 to 200 ms tx-clk tx-data bs1 bs2 (bs2 flag = 0) bs2 (bs2 flag = 1) bs3 x 1 2 224 225 127 ms (54.2 ms) 1.953 x n ms (0.833 x n ms) 1.953 x m ms (0.833 x m ms) preamble mode rst x > 2 ms for external system clock operation or during continuous oscillations x > 900 ms for internal oscillator operation immediately after power is applied or backup is released (v = 1.5 to 3.5 v) x > 1.5 s for internal oscillator operation immediately after power is applied or backup is released (v < 1.5 v) dd dd 7) + 1 tx-clk cycles to complete. when the 225 tx-clk cycles have been received, bs1, bs2 and bs3 are set and device operation transfers to pream- ble mode.
SM8211m nippon precision circuits? preamble mode preamble mode is a continuous 544-bit long period. if neither a preamble pattern, rate error nor sync code is detected during this period, operation transfers to idle mode. if a preamble pattern is detected, the preamble mode 544-bit long period is recommenced. if a rate error is detected, device operation transfers to idle mode. (a single error occurs when two active edges occur in the received signal on sig-in within 1-bit unit time. a rate error occurs when the number of errors in the error counter equals the error thresh- old set by ?gs er0 to er2. the error counter is reset when a preamble pattern is detected.) if the sync code is detected, syn-val goes high and operation transfers to lock mode. (if an error of 2 bits or less occurs, the detected word is recognized as the sync code.) figure 4. idle mode timing figure 5. preamble pattern sequence bs1 bs2 (bs2 flag = 0) bs2 (bs2 flag = 1) bs3 1.953 x n ms (0.833 x n ms) 1.953 x m ms (0.833 x m ms) 62.5 ms (26.7 ms) 1062.5 ms (453.3 ms) receive timing ... 1 0 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ... counting error bit preamble signal preamble count starts count reset to 0 preamble count restarts preamble detected x idle mode in idle mode, a check is made for the presence of a preamble signal when the rf intermittent-duty con- trol signals (bs1, bs2, bs3) for battery saving are active. if a preamble pattern is detected, operation immediately transfers to preamble mode. if a pream- ble pattern is not detected, intermittent-duty opera- tion continues. a preamble pattern is detected when either a 101010 or 010101 6-bit pattern is detected. since there is a reasonable probability that this simple pattern can occur during a valid communicated signal (data, not preamble), this 6-bit pattern makes returning to pre- amble mode easier. this is useful for cases where weak electric ?lds, noise or other temporary inter- ference cause device operation to transfer to idle mode. further, if a sync code is detected within one cycle after device operation has transferred from lock mode, device operation returns to lock mode. (if ?g bs2 is 0, pin bs2 does not go high during the cycle after device operation has transferred from lock mode.)
SM8211m nippon precision circuits?0 lock mode if the sync code is detected during the preamble period, device operation transfers to lock mode and bs1 goes low. bs1 then goes high again under frame timing, where the frame number is set by ?gs ff0 to ff2, and the 24 addresses are compared with id-rom (if the frame number is 0, bs1 stays high). if errors of 2 bits or less occur, the address is still recognized. since there are two code words per frame, this check is done twice. when one of the 24 addresses does not match, bs1 goes low and the device waits for the next sync code receive timing. if the sync code is still not detected after two consecutive attempts, device oper- ation transfers to idle mode, except during message reception where operation stays in lock mode. if the sync code is not detected on the second attempt, but instead a pattern forming a preamble is detected, device operation transfers to preamble mode and not idle mode (preamble mode is more advantageous for sync code detection). figure 6. operating mode transition diagram switch-on mode preamble mode idle mode lock mode a b c d e f g a: after rst goes low, id code is read in sync with tx-clk b: rate error or, within a fixed period, preamble pattern or sync code not detected c: preamble pattern detected d: sync code detected 1 cycle immediately after transferring from lock mode e: sync code not detected on 2 consecutive attempts f: same as e, but preamble pattern detected on the second attempt g: sync code detected when one of the 24 addresses does match, add- det goes high for the duration of the next code word period and the corresponding 5-bit address information is transmitted to the cpu on rx-data in sync with rx-clk. when the address informa- tion is con?med, bs1 is held high and the mes- sage is received. the 20-bit error-corrected message data, a 2-bit error correction result code and an even- parity bit form a 23-bit word that is sent to the cpu on rx-data in sync with rx-clk. when an incoming message spans two or more batches, addi- tional sync code detection occurs during sync code receive timing. message reception ends when an address code or idle code is detected, or when interrupted using the break input. when message reception ends, bs1 goes low and the device waits for either the address detect timing of the next frame or the sync code receive timing.
SM8211m nippon precision circuits?1 figure 7. lock mode timing (frame id number 3) receive code bs1 1.953 x n ms at 512 bps 0.833 x n ms at 1200 bps syn-val break add-det bs2 (flag bs2 = 1) bs3 receive code bs1 syn-val break add-det bs2 (flag bs2 = 1) bs3 icw syn icw add mes mes icw add mes mes mes mes icw icw icw add mes syn mes mes mes mes icw icw add mes mes mes mes icw add mes add mes syn mes syn mes icw icw icw icw add mes mes mes mes mes mes mes mes mes syn mes mes mes icw add mes mes mes mes icw add mes mes icw icw icw syn 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1.953 x n ms at 512 bps 0.833 x n ms at 1200 bps 1.953 x m ms at 512 bps 0.833 x m ms at 1200 bps 1.953 x m ms at 512 bps 0.833 x m ms at 1200 bps address does not match break time break detection to data halt delay time (2 bits max)
SM8211m nippon precision circuits?2 address/flag data transmission (cpu to SM8211m) to form 32-bit code words representing the address information which is then stored in ram. this address information is then compared with the received data to determine correct addressing. if the number of addresses used is less than six, the same address should be repeated as many times as necessary to cancel the remaining addresses. also, each 18-bit address should be input msb ?st. the tx-clk cycle and corresponding address data bits are shown in table 4, and the function of each ?g is shown in tables 5 to 13. table 4. address/?g transmit format tx clock data bit tx clock data bit tx clock data bit tx clock data bit tx clock data bit tx clock data bit tx clock data bit tx clock data bit tx clock data bit 1 0 27 fl1 53 0 79 ab3 105 ac9 131 ad15 157 0 183 0 209 af1 2 ss 28 fl0 54 0 80 ab2 106 ac8 132 ad14 158 0 184 0 210 af0 3 s1 29 er2 55 0 81 ab1 107 ac7 133 ad13 159 0 185 0 211 0 4 s0 30 er1 56 0 82 ab0 108 ac6 134 ad12 160 0 186 0 212 0 5 lbo 31 er0 57 0 83 0 109 ac5 135 ad11 161 ae17 187 0 213 0 6 ff2 32 0 58 0 84 0 110 ac4 136 ad10 162 ae16 188 0 214 0 7 ff1 33 aa17 59 0 85 0 111 ac3 137 ad9 163 ae15 189 0 215 0 8 ff0 34 aa16 60 0 86 0 112 ac2 138 ad8 164 ae14 190 0 216 0 9 inv 35 aa15 61 0 87 0 113 ac1 139 ad7 165 ae13 191 0 217 0 10 bs2 36 aa14 62 0 88 0 114 ac0 140 ad6 166 ae12 192 0 218 0 11 0 37 aa13 63 0 89 0 115 0 141 ad5 167 ae11 193 af17 219 0 12 0 38 aa12 64 0 90 0 116 0 142 ad4 168 ae10 194 af16 220 0 13 0 39 aa11 65 ab17 91 0 117 0 143 ad3 169 ae9 195 af15 221 0 14 pl5 40 aa10 66 ab16 92 0 118 0 144 ad2 170 ae8 196 af14 222 0 15 pl4 41 aa9 67 ab15 93 0 119 0 145 ad1 171 ae7 197 af13 223 0 16 pl3 42 aa8 68 ab14 94 0 120 0 146 ad0 172 ae6 198 af12 224 0 17 pl2 43 aa7 69 ab13 95 0 121 0 147 0 173 ae5 199 af11 225 0 18 pl1 44 aa6 70 ab12 96 0 122 0 148 0 174 ae4 200 af10 19 pl0 45 aa5 71 ab11 97 ac17 123 0 149 0 175 ae3 201 af9 20 rf5 46 aa4 72 ab10 98 ac16 124 0 150 0 176 ae2 202 af8 21 rf4 47 aa3 73 ab9 99 ac15 125 0 151 0 177 ae1 203 af7 22 rf3 48 aa2 74 ab8 100 ac14 126 0 152 0 178 ae0 204 af6 23 rf2 49 aa1 75 ab7 101 ac13 127 0 153 0 179 0 205 af5 24 rf1 50 aa0 76 ab6 102 ac12 128 0 154 0 180 0 206 af4 25 rf0 51 0 77 ab5 103 ac11 129 ad17 155 0 181 0 207 af3 26 fl2 52 0 78 ab4 104 ac10 130 ad16 156 0 182 0 208 af2 after device reset initialization, the address and ?g data is transmitted from the cpu on tx-data in 225 cycles in sync with the falling edge of tx-clk. (see the description in ?witch-on mode?. the SM8211m supports six independent addresses (identi?d as a, b, c, d, e and f). using these, it is possible to cover all kinds of group calls. the address data for each of the six addresses com- prises an 18-bit address plus two function bits used to select one of four sub-addresses. then, one msb bit (0 for address signals), ten bch(31,21) format generated check bits and an even-parity bit are added
SM8211m nippon precision circuits?3 1. = don? care table 5. flag functions flag function ss receive mode set on/off. on when 1. s0, s1 one of eight operating conditions select (with lbo when ss is 1) lbo 512/1200 bps speed select. 512 bps when 1. ff0 to ff2 frame number select inv signal input (sig-in) normal/inverse select. normal when 0. bs2 bs2 output signal mode select pl0 to pl5 bs3 output signal rising-edge setup time for receive timing rf0 to rf5 bs1 output signal rising-edge setup time for receive timing fl2 internal digital ?ter on/off. on when 1. fl0, fl1 digital ?ter parameter select (when fl2 is 1) er0 to er2 rate error detection threshold select table 6. receive mode set ?gs 1 ss s1 s0 lbo set ?gs pl5 pl4 pl3 pl2 pl1 pl0 rf5 rf4 rf3 rf2 rf1 rf0 fl2 fl1 fl0 er2 er1 er0 1000111101001010101001 1010111101001100101001 1100111101001110101001 1110111101010001000001 1001011011000100101001 1011011011000101101001 1101011011000110101001 1111011011000111000001 0 0 all other combinations not set automatically 0 1 table 7. baud rate ?g lbo baud rate 0 1200 bps 1 512 bps table 8. input polarity ?g inv polarity 0 normal 1 inverse table 9. bs2 ?g bs2 bs2 operating mode 0 see the description in section ?attery saving (bs1, bs2, bs3) 1
SM8211m nippon precision circuits?4 1. note that (bs3 rising-edge setup time) - (bs1 rising-edge setup time) should be 3 2. 1. = don? care table 10. frame number ?gs ff2 ff1 ff0 frame number 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 table 11. pll setup time ?gs/bs1 rising-edge setup time ?gs 1 pl5 (rf5) pl4 (rf4) pl3 (rf3) pl2 (rf2) pl1 (rf1) pl0 (rf0) pll setup time (bs1 rising-edge setup time) lbo = 0 lbo = 1 000000 0.000 ms 0.000 ms 000001 0.833 ms 1.953 ms 000010 1.667 ms 3.906 ms 011111 25.833 ms 60.547 ms 100000 26.667 ms 62.500 ms 100001 27.500 ms 64.453 ms 111101 50.833 ms 119.141 ms table 12. digital ?ter constant set ?gs 1 fl2 fl1 fl0 filter constant 0 digital ?ter not used 1 0 0 filter constant 1 1 0 1 filter constant 2 1 1 0 filter constant 3 1 1 1 filter constant 4 table 13. rate error detection set ?gs er2 er1 er0 rate error threshold 0 0 0 count = 1 0 0 1 count = 2 0 1 0 count = 3 0 1 1 count = 4 1 0 0 count = 5 1 0 1 count = 6 1 1 0 count = 7 1 1 1 count = 8
SM8211m nippon precision circuits?5 received data transmission (SM8211m to cpu) in lock mode, if the receive data for the frame is rec- ognized as one of the 24 addresses with 2 bit errors or less, then add-det goes high for the duration figure 8. received address transmit timing rx-data 1 codeword internal bit clock add-det rx-clk 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 a0 a1 a2 a3 a4 detected address codeword of the next code word period and the corresponding 5-bit address information is transmitted to the cpu on rx-data in sync with rx-clk. table 14. address set ?gs a0 a1 a2 a3 a4 address function a0 a1 a2 a3 a4 address function 00100 a a call 00001 d a call 10100 b call 10001 b call 01100 c call 01001 c call 11100 d call 11001 d call 00010 b a call 00101 e a call 10010 b call 10101 b call 01010 c call 01101 c call 11010 d call 11101 d call 00110 c a call 00011 f a call 10110 b call 10011 b call 01110 c call 01011 c call 11110 d call 11011 d call
SM8211m nippon precision circuits?6 when an address is detected, the next 32-bit data code word is received. the bch(31,21) format error check bits are checked and if a 1-bit or two consecu- tive bit errors occur, they are corrected. two random bit errors, or three or more bit errors are not cor- rected. if the corrected data msb is 1, the data is rec- cpu interface syn-val if a sync code is detected with two bit errors or less during sync code detection timing while in preamble, lock or idle mode, syn-val goes high for the duration of the next batch (544 bits long). add-det if frame data is received and recognized with two bit errors or less while in lock mode, add-det goes high for the duration of the next code word period. if an address is detected in the second code word in the frame, add-det stays high for the duration of two code word periods. figure 9. received message transmit timing table 15. error count ?gs e0 e1 error count 0 0 no errors 1 0 1-bit error 0 1 two consecutive bit errors 11 two random, or three or more bit errors rx-data 1 codeword internal bit clock rx-clk 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 received message codeword pe e1 e0 20-bit error-corrected message data ognized as a message, data reception continues and the corrected message data and error check ?gs are sent to the cpu. if the msb is 0, the data is recog- nized as an address signal or idle code and data reception or data transmission to the cpu is halted. 1. the even-parity check is performed on the data before error correction. table 16. parity check ?g pe even-parity check result 1 0 no errors 1 an error occurred break on a rising edge of break, message reception and received message transmission are halted. after a break interrupt, the device waits for frame address detection or sync code detection timing. this func- tion is useful in cases of continuing message recep- tion, because without sync code or other detection taking place the received data would be deemed to have many errors.
SM8211m nippon precision circuits?7 extended reset when rst goes low for 1 to 2 ms or longer, bs1 and bs3 together go high. approximately 1 to 2 ms after rst goes high, device operation continues. when rst is low for less than 200 ms when rst is low for more than 200 ms if the rst low-level pulsewidth exceeds 200 ms, the parameters for switch-on mode should be quickly set over again as soon as rst returns high. for internal oscillator operation, rst goes low for 1 ms or longer immediately after power is applied or just after a b a ckup release. after rst returns figure 10. extended reset timing figure 11. extended reset timing ( 3 200 ms) bs1 bs3 1 to 2 ms rst 1 to 2 ms tx-clk tx-data rst bs1 bs3 data > 200 ms 1 to 200 ms bs3 can also follow the dashed line during this interval. this function is useful for checking the rf stage cir- cuits. after rst goes high, the device waits for the id code input. high, a wait time of approximately 900 ms (v dd = 1.5 to 3.5 v) or 1.5 s (v dd < 1.5 v) should be observed before operation starts.
SM8211m nippon precision circuits?8 power save control when b a ckup goes low, the internal operation stops and all outputs go high impedance. when power save mode is released for normal operation, switch-on mode internal initialization and id code re-setting is required. the xt clock and tx-clk timing when b a ckup goes low is described below. tx-data when not loading after b a ckup has gone low, the xt clock should be maintained for the equivalent time of 65 bits or longer. input signal digital processing (digital filter) in pagers, two baud rates, 512 and 1200 bps, are in use. the current method of ensuring the most suit- able reception conditions is to substitute rf-stage lpf constants that are proportional to the baud rate. in the SM8211m, digital processing of the signal input deals with both baud rates without substituting rf-stage lpf constants. with this digital processing, a particularly small rise in the rate error probability can be expected. the digital processing can be set on or off using ?g fl2, and when on, there are four ?ter constant settings that can be set using ?gs fl0 and fl1 to obtain the most suitable reception conditions in a ?xible manner. (see table 12.) figure 12. tx-data load timing xt tx-clk rst 1 bit equivalent time backup enable (internal) backup tx-data loading during tx-data loading, tx-clk should be maintained and not stopped until the id code is read in. also, the xt clock should be maintained until after the equivalent time of 1 bit after the id code is read in (150 cycles at 512 bps and 64 cycles at 1200 bps). system clock the SM8211m operates using a 76.8 or 153.6 khz system clock. the clock can be set up using a crystal oscillator or an externally input clock. for crystal oscillator clocks, only a crystal needs to be connected between xt and xtn. the oscillator ampli?r, feedback resistor and oscillator capacitor are all built-in. for externally input clocks, the clock is connected to xt through a 100 pf to 0.1 m f coupling capacitor. in both cases, crystal oscillator and external clock, a supply decoupling capacitor of 1000 pf to 0.1 m f should be connected between xvdd and vss. also, the output on xtn should not be used as a clock to drive an external device.
SM8211m nippon precision circuits?9 flowcharts bs1 = bs3 = low switch on preamble idle bit clock counter reset (t = 0) bs3 output timing bit clock count increment (t = t + 1) bs3 = high preamble pattern bs1 = bs2 = high (bs1 = high) bs2 = low (bs2 = high) bs1 = bs3 = low tx-clk count reset (t = 0) tx-clk increment (t = t + 1) id code and flags read in t = 225 id code and flags set bs3 = high bs1 = bs2 = high (bs1 = high) bs2 = low (bs2 = high) preamble idle lock preamble sync code detected rate error t = 544 bs1 = bs3 = low (bs1 = bs2 = bs3 = low) just transferred from lock mode preamble present receive timing finished bs1 = bs3 = low (bs1 = bs2 = bs3 = low) sync code detected syn-val = high no no no yes yes yes no no no no yes yes yes no no no no no yes yes yes yes yes parentheses indicate operation with flag bs2 = 1. rst = low rst = high
SM8211m nippon precision circuits?0 lock frame = 0 bs1 = bs3 = low (bs1 = bs2 = bs3 = low) address detected message receive flag = 1 add-det = high address information transmit sync code timing frame timing message/address message transmit bs2 = low bs1 = bs3 = low message/address valid address (bs2 = high) bs1 = bs3 = low frame = 7 frame timing = frame frame timing < frame sync code timing message receive flag = 0 bs1 = high, bs3 = high setup times for frames bs1 = high, bs3 = high setup times for sync code timing a yes no b no yes yes no c yes no address message message address yes no e no yes
SM8211m nippon precision circuits?1 break input wait until next code word frame timing = frame yes no b d message receive flag = 0 and message halts within 2 bits of time idle preamble e sync code detected syn-val = high message receive flag a syn-val = high syn-val = low preamble present message receive flag bs1 = bs3 = low (bs1 = bs2 = bs3 =low) c yes no yes no no yes 1 0 0 1
SM8211m nippon precision circuits?2 nippon precision circuits inc. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. nippon precision circuits inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. applications for any devices shown in this data sheet are for illustration only and nippon precision circuits inc. makes no claim or warranty that such applications will be suitable for the use speci?d without further testing or modi?ation. the products described in this data sheet are not intended to use for the apparatus which in?ence human lives due to the failure or malfunction of the products. customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. customers shall not export, directly or indirectly, any products without ?st obtaining required licenses and approvals from appropriate government agencies. nippon precision circuits inc. 4-3, fukuzumi 2-chome koto-ku, tokyo 135-8430, japan telephone: 03-3642-6661 facsimile: 03-3642-6698 nc9402de 1995.04 nippon precision circuits inc. typical applications paging receiver system sp rf stage decoder alert SM8211m decoder ic cpu amplifier id-rom d/d converter rf waveform generator lcd driver lcd supply display

▲Up To Search▲

Price & Availability of SM8211

	To Download SM8211 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .